Design and Development of CPLD Based on Low Power Pipelined 64-bit RISC Processor with Unbiased Floating Point Unit

RISC is a design philosophy where it reduces the complexity of the instruction set, which will reduce the amount of space, time, cost, power and heat etc.,. This processor is developed especially for Arithmetic operations of both fixed and floating point numbers, branch and logical functions. Pipelining would not flush when branch instruction occurs as it is implemented using dynamic branch prediction. This will increase flow in instruction pipeline and high effective performance. In RTL coding one can reduce the dynamic power by using clock gating technique. In this paper also implement unbiased double precision floating point arithmetic operations like addition, subtraction, multiplication and division. The outcome values of these operations stored in the registers and they can retrieve from the same when needed. The low power RISC processor with unbiased double precision floating point unit is designed without any complication, because the power reduction can do in front end technique. The necessary code is written in the hardware description language Verilog HDL and it is implemented on Altera MAXV CPLD device. This architecture has become indispensable and increasingly important in many applications like signal processing, graphics and medical by using floating point operations.